Processors working on a multiple data in parallel exist, such as for example Digital Signal Processors (DSP), Single Instruction on Multiple Data (SIMD) processors, Long Instruction Word (LIW) processors, or vector processors, i.e. designed to perform operations on multiple numbers (representing vectors or arrays) during a single clock cycle.
Such processors need to be able to read and write a set of data at the same time as quickly as possible.
This data may be stored in various memories which need to be used optimally to maximum high-speed access.
Using a storage system intended to be timed by a clock signal and comprising a plurality of memories is thus known.
Each memory comprises a certain number of input and output ports. Each input port is intended to receive a request for access to one of the memory locations, tagged by the address thereof, referred to as the local address, in the memory. The memory is intended to receive local requests at each clock cycle and to respond thereto in a predefined number of clock cycles. The memory is further intended to submit, at the end of said clock cycle(s), any responses on the output ports thereof. In this way, a memory can only receive, for each clock cycle, a limited number of local requests, at most equal to the number of input ports of this memory.
A conventional type of memory is for example a single-port (one input port and one associated output port) or double-port (two input ports and two associated output ports) Random Access Memory (RAM).
The storage system further comprises input ports and one or a plurality of output ports. Each input port is intended to receive, at each clock cycle, a request to access a location of one of the memories. This request indicates a global address structured as if the storage system formed a single memory. Using a correspondence function associating each global address with one of the memories and with a local address in this memory is thus known.
During the same clock cycle, the storage system may receive on the input ports thereof a greater number of requests for access to the same memory than that which can be received by the memory on the input ports thereof. A conflict thus arises since the memory will not be able to receive all these requests in the same clock cycle.
It is thus necessary to implement an effective method for handling requests to reduce the frequency of conflicts.
A number of publications exist, describing methods for handling memory access requests, including:                the thesis by Eero Aho entitled “Design and Implementation of Parallel Memory Architectures”, and published in 2006 in Tampere University of Technology, Publication 641,        the article by Kimmo Kuusilinna et al. entitled “Configurable parallel memory architecture for multimedia computers”, and published in 2002 in Journal of Systems Architecture 47 (2002) 1089-1115, and        the article by Dionysios Reisis et al. entitled “Conflict-Free Parallel Memory Accessing Techniques for FFT Architectures”, and published in 2008 in IEEE Transactions on circuits and systems, I—Regular papers, vol. 55, No. 11, Dec. 2008.        
These methods all suggest optimising the correspondence function as a function for the predictable distribution of memory access.
These methods for handling requests involve the problem of not being very effective for more complex applications, such as Fast Fourier Transform (FFT) with a radix changing over time according to the size of the vectors on the basis whereof the FFT is computed, or applications wherein random or near-random locations are accesses. In this way, memory access is difficult to predict such that it is not possible to optimise the correspondence function.